Western Digital Announces Four Bit Per Cell 64-Layer 3D NAND Flash
by Billy Tallis on July 25, 2017 8:00 AM EST
Western Digital's SanDisk subsidiary and Toshiba have a long history of jointly developing and manufacturing NAND flash memory. While that relationship has been strained by Toshiba's recent financial troubles and attempts to sell of their share of the memory business, the companies are continuing to develop new flash memory technology and are still taking turns making new announcements. In recent months both companies have started sampling SSDs using their 64-layer BiCS3 TLC 3D NAND and have announced that their next generation BiCS4 3D NAND will be a 96-layer design.
Yesterday Western Digital made a small announcement about their other main strategy for increasing density: storing more bits per memory cell. Western Digital will introduce four bit per cell QLC parts built on their 64-layer BiCS3 process, with a capacity of 768Gb (96GB) per die. This is a substantial increase over the 512Gb BiCS3 TLC parts that will be hitting the market soon, and represents not only an increase in in bits stored per memory cell but an increase in the overall size of the memory array. These new 3D QLC NAND parts are clearly intended to offer the best price per GB that Western Digital can manage, but Western Digital claims performance will still be close to that of their 3D TLC NAND. Western Digital's announcement did not mention write endurance, but Toshiba's earlier announcement of 3D QLC NAND claimed endurance of 1000 program/erase cycles, far higher than industry expectations of 100-150 P/E cycles for 3D QLC and comparable to 3D TLC NAND.
Western Digital has not announced any specific products based on QLC NAND flash, but they will be exhibiting both removable media and SSDs using QLC NAND at Flash Memory Summit August 8-10. Western Digital's CTO will be delivering a keynote presentation at FMS on August 8, so more details are likely to be revealed in two weeks.
Western Digital's roadmaps also include plans for QLC parts on their 96-layer BiCS4 process, with capacities up to 1Tb (128GB) per die. BiCS4 production is scheduled to ramp up over 2018 and 2019 with the QLC parts expected to arrive later in the cycle, so Western Digital's first-generation 3D QLC based on the BiCS3 process will probably be their highest-density flash memory in mass production for over a year.
Source: Western Digital
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Bullwinkle J Moose - Tuesday, July 25, 2017 - link
FINALLY, I can enjoy reading comments about the subject matter!I hate scrolling across the entire page to find ZERO comments about the subject at hand
Nothing but worthless comments on advertising on that last page
Now then,..........um.......what was the subject?
jasonelmore - Tuesday, July 25, 2017 - link
i don't read ads, i contribute to the website by giving everyone my knowledge in the comments! you guys really owe me! /sedzieba - Wednesday, July 26, 2017 - link
If the layer count remains the same, why does adding an additional bit per cell not result in a straight doubling in capacity per die? Do the cells themselves have to be physically larger to handle the finder differences in charge required, or are more cells dedicated to parity checking?DanNeely - Wednesday, July 26, 2017 - link
that's what happened with SLC to MLC flash. TLC to QLC is 3 bits/cell to 4 bits/cell; or 33% more capacity. It might be clearer if you work a tiny example. If you have 8 flash cells, with SLC you have 8 bits or 1 byte of capacity. MLC is 16 bits/2bytes or 100% more. TLC is 24bits/3bytes or 50% more. QLC is 32 bits/4 bytes for an additional 33%.That's the raw gain anyway, end user products will potentially have less due to using more of the die as spare area and potentially needing a more data intensive ECC mechanism.
You might need a bit more control circuitry too; not sure on that but a countvailing factor is that a significant chunk of it is fixed in size to communicate with the controller chip which is why a chip half the capacity at a given process is more half the size of the bigger one. (This limits parallelism in lower end devices and is a major factor in why minimum SSD sizes grow with each new generation. A minimum of parallelism is needed for reasonable performance and the smallest commercially viable flash chip size keeps getting larger.)
Alexvrb - Wednesday, July 26, 2017 - link
I'm all for QLC for a secondary drive. I wouldn't use it for important stuff, I've got my OS and games on an Evo... but for mass storage it's perfect. Even if it's not quite as reliable as a good TLC drive, it will still be far more reliable than the vast majority of mechanical drives (which I am currently using for mass storage).