The Cortex-A77 µarch: Going For A 6-Wide* Front-End

The Cortex-A76 represented a clean-sheet design in terms of its microarchitecture, with Arm implementing from scratch the knowledge and lessons of years of CPU design. This allowed the company to design a new core that was forward-thinking in terms of its microarchitecture. The A76 was meant to serve as the baseline for the next two designs from the Austin family, today’s new Cortex-A77 as well next year’s “Hercules” design.

The A77 pushes new features with the primary goals of increasing the IPC of the microarchitecture. Arm’s goals this generation is a continuation of focusing on delivering the best PPA in the industry, meaning the designers were aiming to increase the performance of the core while maintaining the excellent energy efficiency and area size characteristics of the A76 core.

In terms of frequency capability, the new core remains in the same frequency range as the A76, with Arm targeting 3GHz peak frequencies in optimal implementations.

As an overview of the microarchitectural changes, Arm has touched almost every part of the core. Starting from the front-end we’re seeing a higher fetch bandwidth with a doubling of the branch predictor capability, a new macro-OP cache structure acting as an L0 instruction cache, a wider middle core with a 50% increase in decoder width, a new integer ALU pipeline and revamped load/store queues and issue capability.

Dwelling deeper into the front-end, a major change in the branch predictor was that its runahead bandwidth has doubled from 32B/cycle to 64B/cycle. Reason for this increase was in general the wider and more capable front-end, and the branch predictor’s speed needed to be improved in order to keep up with feeding the middle-core sufficiently. Arm instructions are 32bits wide (16b for Thumb), so it means the branch predictor can fetch up to 16 instructions per cycle. This is a higher bandwidth (2.6x) than the decoder width in the middle core, and the reason for this imbalance is to allow the front-end to as quickly as possible catch up whenever there are branch bubbles in the core.

The branch predictor’s design has also changed, lowering branch mispredicts and increasing its accuracy. Although the A76 already had the a very large Branch Target Buffer capacity with 6K entries, Arm has increased this again by 33% to 8K entries with the new generation design. Seemingly Arm has dropped a BTB hierarchy: The A76 had a 16-entry nanoBTB and a 64-entry microBTB – on the A77 this looks to have been replaced by a 64-entry L1 BTB that is 1 cycle in latency.

Another major feature of the new front-end is the introduction of a Macro-Op cache structure. For readers familiar with AMD and Intel’s x86 processor cores, this might sound familiar and akin to the µOP/MOP cache structures in those cores, and indeed one would be correct in assuming they have the similar functions.

In effect, the new Macro-OP cache serves as a L0 instruction cache, containing already decoded and fused instructions (macro-ops). In the A77’s case the structure is 1.5K entries big, which if one would assume macro-ops having a similar 32-bit density as Arm instructions, would equate to about 6KB.

The peculiarity of Arm’s implementation of the cache is that it’s deeply integrated with the middle-core. The cache is filled after the decode stage (in a decoupled manner) after instruction fusion and optimisations. In case of a cache-hit, then the front-end directly feeds from the macro-op cache into the rename stage of the middle-core, shaving off a cycle of the effective pipeline depth of the core. What this means is that the core’s branch mispredicts latency has been reduced from 11 cycles down to 10 cycles, even though it has the frequency capability of a 13 cycle design (+1 decode, +1 branch/fetch overlap, +1 dispatch/issue overlap). While we don’t have current direct new figures of newer cores, Arm’s figure here is outstandingly good as other cores have significantly worse mispredicts penalties (Samsung M3, Zen1, Skylake: ~16 cycles).

Arm’s rationale for going with a 1.5K entry cache size is that they were aiming for an 85% hit-rate across their test suite workloads. Having less capacity would take reduce the hit-rate more significantly, while going for a larger cache would have diminishing returns. Against a 64KB L1 cache the 1.5K MOP cache is about half the area in size.

What the MOP cache also allows is for a higher bandwidth to the middle-core. The structure is able to feed the rename stage with 64B/cycle – again significantly higher than the rename/dispatch capacity of the core, and again this imbalance with a more “fat” front-end bandwidth allows the core to hide to quickly hide branch bubbles and pipeline flushes.

Arm talked a bit about “dynamic code optimisations”: Here the core will rearrange operations to better suit the back-end execution pipelines. It’s to be noted that “dynamic” here doesn’t mean it’s actually programmable in what it does (Akin to Nvidia’s Denver code translations), the logic is fixed to the design of the core.

Finally getting to the middle-core, we see a big uplift in the bandwidth of the core. Arm has increased the decoder width from 4-wide to 6-wide.

Correction: The Cortex A77’s decoder remains at 4-wide. The increased middle-core width lies solely at the rename stage and afterwards; the core still fetches 6 instructions, however this bandwidth only happens in case of a MOP-cache hit which then bypasses the decode stage. In MOP-cache miss-cases, the limiting factor is still the decoder which remains at 4 instructions per cycle.

The increased width also warranted an increase of the reorder buffer of the core which has gone from 128 to 160 entries. It’s to be noted that such a change was already present in Qualcomm’s variant of the Cortex-A76 although we were never able to confirm the exact size employed. As Arm was still in charge of making the RTL changes, it wouldn’t surprise me if was the exact same 160 entry ROB.

Arm's Cortex's CPUs: Continuing on A76's Success The Cortex-A77 µarch: Added ALUs & Better Load/Stores
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  • Raqia - Tuesday, May 28, 2019 - link

    Another interesting development in the big AX CPUs is that they've moved from a more complex cache hierarchy in the A10 to a 2 level hierarchy with a much bigger L2 since the A11 that had better bandwidth and latency; L1's were also further boosted in size and bandwidth in the A12. This likely accounts for the continuation of growth in single threaded benchmark scores but seems to indicate that the CPU complex is oriented toward client type workloads.

    ARM has gone full steam ahead with more multi-processing oriented cache designs with some SoCs sporting a further layer of L4 cache and server designs sporting sophisticated un-cores. Their ambitions seem rather different than Apple's and this year's A77's will likely be implemented into servers designs sometime soon.

    Apple's 3-wide OoOE little cores continue to be even more impressive than their big cores, and hold their own against the A73 in performance with much higher efficiency. One wonders if the 2-wide A73 or even the A75 could be tweaked and underclocked to be the "little" in future designs. It certainly fits the bill in terms of die area.
  • peevee - Tuesday, May 28, 2019 - link

    "The results is that the Kirin 980 as well as the Snapdragon 855 both represented major jumps over their predecessors. Qualcomm has proclaimed a 45% leap in CPU performance compared to the previous generation Snapdragon 855 with Cortex-A76 cores, the biggest generational leap ever."

  • peevee - Tuesday, May 28, 2019 - link

    "In the A77’s case the structure is 1.5K entries big, which if one would assume macro-ops having a similar 32-bit density as Arm instructions, would equate to about 48KB."

    You mean Kb, right? And of course this assumption is nonsense.
  • peevee - Tuesday, May 28, 2019 - link

    "web-browsing is the killer-app that happens to be floating point heavy"

    Why? Because ECMAScript has just one number type?
    I suspect WebAssembly would eliminate this problem.
  • ballsystemlord - Tuesday, May 28, 2019 - link

    Spelling and grammar corrections:

    "Having less capacity would take reduce the hit-rate more significantly, while going for a larger cache would have diminishing returns."
    Extra word "take":
    "Having less capacity would reduce the hit-rate more significantly, while going for a larger cache would have diminishing returns."

    "...and again this imbalance with a more "fat" front-end bandwidth allows the core to hide to quickly hide branch bubbles and pipeline flushes."
    More extra words "to hide":
    "...and again this imbalance with a more "fat" front-end bandwidth allows the core to quickly hide branch bubbles and pipeline flushes."
  • sireangelus - Tuesday, May 28, 2019 - link

    Are there any news or rumors regarding the succesor of the cortex a55? not even just working on reducing power consumption?
  • tuxRoller - Tuesday, May 28, 2019 - link

    "The combination of the brand-new microarchitecture alongside the major improvements that the 7nm TSMC process node has brought some of the biggest performance and efficiency jumps we’ve ever seen in the industry."

    Or, to paraphrase many a cynical AT commenter: same old incremental improvement, nothing exciting... where's my mr fusion?!!!
  • AshlayW - Tuesday, May 28, 2019 - link

    Can someone tell me how this stacks up to a high-performance X86 core, like Zen or Skylake please? If ARM is so powerful and efficient why are they not developing Desktop CPUs? Is it just because the software ecosystem is dominated by proprietary X86?
  • Wilco1 - Wednesday, May 29, 2019 - link

    The IPC is higher than the latest x86 cores. There are Arm server CPUs which are competitive with Skylake and beat it on HPC applications in super computers. Currently you can buy desktops based on ThunderX2 and Ampere, see .
  • Farfolomew - Thursday, June 6, 2019 - link

    I wish this were talked about more. As awesome as Zen2 is, and as cool as the story is regarding AMD finally getting on level playing field with Intel again (ie, circa 2004), in the back of my mind I find it a bit silly when all the while that's been happening, a better architecture in all regards has managed to catch up and pass x86. That should be where the computing industry focus is, and how Intel+AMD is planning on battling that threat.

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