The Cortex-A77 µarch: Going For A 6-Wide* Front-End

The Cortex-A76 represented a clean-sheet design in terms of its microarchitecture, with Arm implementing from scratch the knowledge and lessons of years of CPU design. This allowed the company to design a new core that was forward-thinking in terms of its microarchitecture. The A76 was meant to serve as the baseline for the next two designs from the Austin family, today’s new Cortex-A77 as well next year’s “Hercules” design.

The A77 pushes new features with the primary goals of increasing the IPC of the microarchitecture. Arm’s goals this generation is a continuation of focusing on delivering the best PPA in the industry, meaning the designers were aiming to increase the performance of the core while maintaining the excellent energy efficiency and area size characteristics of the A76 core.

In terms of frequency capability, the new core remains in the same frequency range as the A76, with Arm targeting 3GHz peak frequencies in optimal implementations.

As an overview of the microarchitectural changes, Arm has touched almost every part of the core. Starting from the front-end we’re seeing a higher fetch bandwidth with a doubling of the branch predictor capability, a new macro-OP cache structure acting as an L0 instruction cache, a wider middle core with a 50% increase in decoder width, a new integer ALU pipeline and revamped load/store queues and issue capability.

Dwelling deeper into the front-end, a major change in the branch predictor was that its runahead bandwidth has doubled from 32B/cycle to 64B/cycle. Reason for this increase was in general the wider and more capable front-end, and the branch predictor’s speed needed to be improved in order to keep up with feeding the middle-core sufficiently. Arm instructions are 32bits wide (16b for Thumb), so it means the branch predictor can fetch up to 16 instructions per cycle. This is a higher bandwidth (2.6x) than the decoder width in the middle core, and the reason for this imbalance is to allow the front-end to as quickly as possible catch up whenever there are branch bubbles in the core.

The branch predictor’s design has also changed, lowering branch mispredicts and increasing its accuracy. Although the A76 already had the a very large Branch Target Buffer capacity with 6K entries, Arm has increased this again by 33% to 8K entries with the new generation design. Seemingly Arm has dropped a BTB hierarchy: The A76 had a 16-entry nanoBTB and a 64-entry microBTB – on the A77 this looks to have been replaced by a 64-entry L1 BTB that is 1 cycle in latency.

Another major feature of the new front-end is the introduction of a Macro-Op cache structure. For readers familiar with AMD and Intel’s x86 processor cores, this might sound familiar and akin to the µOP/MOP cache structures in those cores, and indeed one would be correct in assuming they have the similar functions.

In effect, the new Macro-OP cache serves as a L0 instruction cache, containing already decoded and fused instructions (macro-ops). In the A77’s case the structure is 1.5K entries big, which if one would assume macro-ops having a similar 32-bit density as Arm instructions, would equate to about 6KB.

The peculiarity of Arm’s implementation of the cache is that it’s deeply integrated with the middle-core. The cache is filled after the decode stage (in a decoupled manner) after instruction fusion and optimisations. In case of a cache-hit, then the front-end directly feeds from the macro-op cache into the rename stage of the middle-core, shaving off a cycle of the effective pipeline depth of the core. What this means is that the core’s branch mispredicts latency has been reduced from 11 cycles down to 10 cycles, even though it has the frequency capability of a 13 cycle design (+1 decode, +1 branch/fetch overlap, +1 dispatch/issue overlap). While we don’t have current direct new figures of newer cores, Arm’s figure here is outstandingly good as other cores have significantly worse mispredicts penalties (Samsung M3, Zen1, Skylake: ~16 cycles).

Arm’s rationale for going with a 1.5K entry cache size is that they were aiming for an 85% hit-rate across their test suite workloads. Having less capacity would take reduce the hit-rate more significantly, while going for a larger cache would have diminishing returns. Against a 64KB L1 cache the 1.5K MOP cache is about half the area in size.

What the MOP cache also allows is for a higher bandwidth to the middle-core. The structure is able to feed the rename stage with 64B/cycle – again significantly higher than the rename/dispatch capacity of the core, and again this imbalance with a more “fat” front-end bandwidth allows the core to hide to quickly hide branch bubbles and pipeline flushes.

Arm talked a bit about “dynamic code optimisations”: Here the core will rearrange operations to better suit the back-end execution pipelines. It’s to be noted that “dynamic” here doesn’t mean it’s actually programmable in what it does (Akin to Nvidia’s Denver code translations), the logic is fixed to the design of the core.

Finally getting to the middle-core, we see a big uplift in the bandwidth of the core. Arm has increased the decoder width from 4-wide to 6-wide.

Correction: The Cortex A77’s decoder remains at 4-wide. The increased middle-core width lies solely at the rename stage and afterwards; the core still fetches 6 instructions, however this bandwidth only happens in case of a MOP-cache hit which then bypasses the decode stage. In MOP-cache miss-cases, the limiting factor is still the decoder which remains at 4 instructions per cycle.

The increased width also warranted an increase of the reorder buffer of the core which has gone from 128 to 160 entries. It’s to be noted that such a change was already present in Qualcomm’s variant of the Cortex-A76 although we were never able to confirm the exact size employed. As Arm was still in charge of making the RTL changes, it wouldn’t surprise me if was the exact same 160 entry ROB.

Arm's Cortex's CPUs: Continuing on A76's Success The Cortex-A77 µarch: Added ALUs & Better Load/Stores
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  • Thala - Monday, May 27, 2019 - link

    An "A77 7nm SoC" would consist of 4 A77 cores, while "10nm A10" consists of 2 high performance Fusion cores - making the A77 SoC much faster than A10.

    You cannot use single core performance to reason about SoC performance without taking the number of cores into consideration.
  • LiverpoolFC5903 - Tuesday, May 28, 2019 - link

    I wonder why do people make these pointless comparisons. You have an OS that doesn't allow you to do half the things you can do on an Android system, so what exactly is the use of a super high powered soc?

    Can you copy music and movies directly into your flash memory?
    Can you attach external memory using OTG?
    Can you use USB OTG peripherals like gamepads and keyboards?
    Can you install apps/software from outside of Apple's closed ecosystem?
    Can you get pointer support in iOS?
    Can you properly manage the files in your smartphone?
    Can your iphone seamlessly interface with your windows PC?
  • Phynaz - Thursday, May 30, 2019 - link

    Did you know it’s 2019? 2007 wants their Apple hate back.
  • Valis - Thursday, May 30, 2019 - link

    And 2007 wants its limited OS back. Not to mention the price for 720p devices.
  • Meteor2 - Monday, June 3, 2019 - link

    It's 2019, and iOS is still as restricted as it ever was.
  • jjj - Monday, May 27, 2019 - link

    Will be interesting to see cloud providers adopting the server version. It's small,it's efficient, it's pretty fast, should be good business.
  • Meteor2 - Monday, June 3, 2019 - link

    Server CPUs seem to take a lot longer to reach market; it's still only A72 and A73 stuff at the moment! Much less money for the necessary investment. But when A76 and A77 does reach the server (and maybe the desktop?) it's going to be very exciting.
  • Demaniax - Monday, May 27, 2019 - link

    Can anyone tell me how to learn all of these things ? I mean how does a CPU made. What is a Pipeline ? What is branch prediction ? And all those things. I want to learn everything. But How ? Is there any online course ?
  • frenchy_2001 - Monday, May 27, 2019 - link
    the links to edx and would be interesting.
    It all depends on what your background is and how serious you are.
    You can find great resources online, but this is a big and very advanced domain, so you may need to follow intro level classes in digital circuits before being able to follow full architecture.
  • suvtab - Tuesday, May 28, 2019 - link

    A book on Computer Architecture ( will be a good start point. I personally recommend David Patterson's classical textbook "Computer Architecture: A Quantitative Approach".

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