Fireside Chat with Ian and Wendell: Ryzen 3000, Zen 2, Navi, Xeon Wby Dr. Ian Cutress on June 14, 2019 9:00 AM EST
The last couple of weeks have been a blitz, with the Computex trade show in Taipei almost immediately followed by E3 in Los Angeles. In both instances, AMD was coming to the fore with news about its next generation products, including detailed microarchitecture as well as product pricing, speeds, feeds, and all the good stuff. I took some time to sit down and chat with Wendell, the host of the Level1Techs YouTube channel, to speak to some of the movement regarding processors in our industry.
Our discussion piggybacked off of AMD’s Gaming Tech Day, held before their E3 presentation. The conversation was free flowing with no set structure; however we do touch upon various topics:
- AMD products for 2019
- Chipset and IO die implementations
- What exactly does Intel do from here
- Redefining the computational paradigm
- New packaging methodologies
- How each vendor approaches benchmark discussions
- Computex Highlights, including the Chinese Hygon/EPYC processor
- Ryzen 9 3950X Pricing and Threadripper
- Hot Chips
Many thanks to Wendell for having me on his channel. Level1Techs is one of the few YouTube channels that specialises in detailed content, and Wendell and I have collaborated on projects before, such as our dive into Threadripper’s scheduling issues.
Let us know if you would like to see more of this sort of content.
- AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome
- AMD 16-Core Ryzen 9 3950X: Up to 4.7 GHz, 105W, Coming September
- AMD Ryzen 3000 APUs: Up to Vega 11, More MHz, Under $150, Coming July 7th
- Intel Cascade Lake Xeon W-3200 Launched: Server Socket, 64 PCIe 3.0 lanes
- AMD Confirms PCIe 4.0 Not Coming to Older Motherboards (X470, X370, B350, A320)
- Spotted at Computex: Let Bygones be Bygons, with a Sugon Hygon
- Intel to Launch New X-Series CPUs this Fall
- AMD Ryzen 3000 Announced: Five CPUs, 12 Cores for $499, Up to 4.6 GHz, PCIe 4.0, Coming 7/7
- Intel Announces 8 Core i9-9900KS: Every Core at 5.0 GHz, All The Time
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hanselltc - Sunday, June 16, 2019 - linkoh HELL YEA.
yankeeDDL - Monday, June 17, 2019 - linkThanks for the open discussion. It's good to hear the thoughts behind all those technical articles every now and then.
Question: after all the Spectre-related mitigations, the improvement in the scheduler in W10 1903, wouldn't it make sense to re-run a CPU comparison using the last could of generations from both AMD and Intel, before we start digging into Ryzen 3xxx and Core 9xxx?
rarson - Tuesday, June 18, 2019 - linkI saw this on Wendell's channel when it was posted, and I really enjoyed it. Especially since I've never heard you talk on camera, Ian. Very insightful video, please do some more of these in the future (AT doesn't even necessarily need to produce their own videos, you could continue doing collaborations with Youtubers like this).
Kougar - Tuesday, June 18, 2019 - linkAwesome video, thank guys! This is exactly the sort of behind the scenes stuff and info that's great to hear about especially with how it ties into the hardware! You two should make this a regular thing after big events!
just4U - Tuesday, June 18, 2019 - linkIt was a excellent video.. You need to do more of these Ian.
Rukur - Wednesday, June 19, 2019 - linkWas an interesting chat. Hope you guys catch up again across the world.
WaltC - Wednesday, June 19, 2019 - linkExcellent! Most interesting...we need...more...!
peevee - Thursday, June 20, 2019 - linkVideo sucks because the talk is not searchable and not easily quotable. Video makes sense when you have something to SHOW, not just to TELL.
peevee - Thursday, June 20, 2019 - linkWendell, speaking about Intel: "chiplets would be implemented years ago" - well, they were, remember Core 2 Quad? And many others for different reasons, including North Bridge and last level cache. This idea is old, and not all that smart as you have to have more SKUs instead of letting user pick and choose different chips for their system (of course you need small sockets to match power and latency of chiplets instead of the current monsters).
ajc9988 - Friday, June 21, 2019 - linkYour comment makes no sense. Even though gluing two cores together long ago happened, you say that it is "not all that smart," while Intel is now looking at doing it in a couple years and incorporating ASICs when they do chiplets this time. The industry is moving as a whole to 2.5D and 3D stacking, which is based on chiplets, in part.
Then you continue on to say they "have to have more SKUs instead of letting user pick and choose different chips for their system (of course you need small sockets to match power and latency of chiplets instead of the current monsters)." Intel with monolithic dies has more SKUs than AMD. That doesn't end with chiplets. In fact, by making the core counts smaller per chiplet, you can drastically increase yields per wafer on smaller process nodes, allowing for the harvesting and binning of those dies, which can easily fill the product stack. Also, more SKUs means more choice for the consumer, rather than less.
Yes, they have to develop ways to get around issues like latency, which AMD has done significant work on with Zen 2. So, you saying it is dumb to do chiplets is irrelevant and shows you lack an understanding of where the industry is going as a whole. Moore's law is dead. We are reaching a point where clock speeds are likely to start regressing, as seen with Intel's 10nm and that AMD said they thought would happen until TSMC figured it out on 7nm. With future nodes, especially 5nm and below at TSMC and 7nm and below at Intel (even though Intel's 10nm has crap on yields), that problem is amplified. To combat that, Intel went wide on architecture, increasing IPC, that way to attempt to make up for the frequency regression. Sunny Cove achieved this well. But, there will be a point where due to yields, likely at 7nm on Intel's process, where the only way to achieve reasonable use of the wafer is to disintegrate the cores into chiplets, bin them, and incorporate them on their specific lines.
Even Foveros uses this disintegration as I/O was moved to the base die, suggesting that those are two different chiplets, just organized in a different way. Yet you cannot even acknowledge that.