Intel Thread Director

One of the biggest criticisms that I’ve levelled at the feet of Intel since it started talking about its hybrid processor architecture designs has been the ability to manage threads in an intelligent way. When you have two cores of different performance and efficiency points, either the processor or the operating system has to be cognizant of what goes where to get the best result from the end-user. This requires doing additional analysis on what is going on with each thread, especially new work that has never been before.

To date, most desktop operating systems operate on the assumption that all cores and the performance of everything in the system is equal.  This changed slightly with simultaneous multithreading (SMT, or in Intel speak, HyperThreading), because now the system had double the threads, and these threads offered anywhere from zero to an extra 100% performance based on the workload. Schedulers were hacked a bit to identify primary and secondary threads on a core and schedule new work on separate cores. In mobile situations, the concept of an Energy Aware Scheduler (EAS) would look at the workload characteristics of a thread and based on the battery life/settings, try and schedule a workload where it made sense, particularly if it was a latency sensitive workload.

Mobile processors with Arm architecture designs have been tackling this topic for over a decade. Modern mobile processors now have three types of core inside – a super high performance core, regular high performance cores, and efficiency cores, normally in a 1+3+4 or 2+4+4 configuration. Each set of cores has its own optimal window for performance and power, and so it relies on the scheduler to absorb as much information as possible to determine the best way to do things.

Such an arrangement is rare in the desktop space - but now with Alder Lake, Intel has an SoC that has SMT performance cores and non-SMT efficient cores. With Alder Lake it gets a bit more complex, and the company has built a technology called Thread Director.

That’s Intel Thread Director. Not Intel Threat Detector, which is what I keep calling it all day, or Intel Threadripper, which I have also heard. Intel will use the acronym ITD or ITDT (Intel Thread Director Technology) in its marketing. Not to be confused with TDT, Intel’s Threat Detection Technology, of course.

Intel Threadripper Thread Director Technology

This new technology is a combined hardware/software solution that Intel has engineered with Microsoft focused on Windows 11. It all boils down to having the right functionality to help the operating system make decisions about where to put threads that require low latency vs threads that require high efficiency but are not time critical.

First you need a software scheduler that knows what it is doing. Intel stated that it has worked extensively with Microsoft to get what they want into Windows 11, and that Microsoft have gone above and beyond what Intel needed. This fundamental change is one reason why Windows 11 exists.

So it’s easy enough (now) to tell an operating system that different types of cores exist. Each one can have a respective performance and efficiency rating, and the operating system can migrate threads around as required. However the difference between Windows 10 and Windows 11 is how much information is available to the scheduler about what is running.

In previous versions of Windows, the scheduler had to rely on analysing the programs on its own, inferring performance requirements of a thread but with no real underlying understanding of what was happening. Windows 11 leverages new technology to understand different performance modes, instruction sets, and it also gets hints about which threads rate higher and which ones are worth demoting if a higher priority thread needs the performance.

Intel classifies the performance levels on Alder Lake in the following order:

  1. One thread per core on P-cores
  2. Only thread on E-cores
  3. SMT threads on P-cores

That means the system will load up one thread per P-core and all the E-cores before moving to the hyperthreads on the P-cores.

Intel’s Thread Director controller puts an embedded microcontroller inside the processor such that it can monitor what each thread is doing and what it needs out of its performance metrics. It will look at the ratio of loads, stores, branches, average memory access times, patterns, and types of instructions. It then provides suggested hints back to the Windows 11 OS scheduler about what the thread is doing, whether it is important or not, and it is up to the OS scheduler to combine that with other information about the system as to where that thread should go. Ultimately the OS is both topologically aware and now workload aware to a much higher degree.

Inside the microcontroller as part of Thread Director, it monitors which instructions are power hungry, such as AVX-VNNI (for machine learning) or other AVX2 commands that often draw high power, and put a big flag on those for the OS for prioritization. It also looks at other threads in the system and if a thread needs to be demoted, either due to not having enough free P-cores or for power/thermal reasons, it will give hints to the OS as to which thread is best to move. Intel states that it can profile a thread in as little as 30 microseconds, whereas a traditional OS scheduler may take 100s of milliseconds to make the same conclusion (or the wrong one).

On top of this, Intel says that Thread Director can also optimize for frequency. If a thread is limited in a way other than frequency, it can detect this and reduce frequency, voltage, and power. This will help the mobile processors, and when asked Intel stated that it can change frequency now in microseconds rather than milliseconds.

We asked Intel about where an initial thread will go before the scheduling kicks in. I was told that a thread will initially get scheduled on a P-core unless they are full, then it goes to an E-core until the scheduler determines what the thread needs, then the OS can be guided to upgrade the thread. In power limited scenarios, such as being on battery, a thread may start on the E-core anyway even if the P-cores are free.

For users looking for more information about Thread Director on a technical, I suggest reading this document and going to page 185, reading about EHFI – Enhanced Hardware Frequency Interface. It outlines the different classes of performance as part of the hardware part of Thread Director.

It’s important to understand that for the desktop processor with 8 P-cores and 8 E-cores, if there was a 16-thread workload then it will be scheduled across all 8 P-cores with 8 threads, then all 8 E-cores with the other 8 threads. This affords more performance than enabling the hyperthreads on the P-cores, and so software that compares thread-to-thread loading (such as the latest 3DMark CPU Profile test) may be testing something different compared to processors without E-cores.

On the question of Linux, Intel only went as far to say that Windows 11 was the priority, and they’re working upstreaming a variety of features in the Linux kernel but it will take time. An Intel spokesperson said more details closer to product launch, however these things will take a while, perhaps months and years, to get to a state that could be feature-parity equivalent with Windows 11.

One of the biggest questions users will ask is about the difference in performance or battery between Windows 10 and Windows 11. Windows 10 does not get Thread Director, but relies on a more basic version of Intel’s Hardware Guided Scheduling (HGS). In our conversations with Intel, they were cagy to put any exact performance differential metrics between the two, however based on understanding of the technology, we should expect to see better frequency efficiency in Windows 11. Intel stated that even though the new technology in Windows 11 will mean threads will move more often than in Windows 10, potentially adding latency, in their testing it wasn’t in any way human perceivable. Ultimately because the Win11 configuration can also optimize for power and efficiency, especially in mobile, Intel puts the win on Windows 11.

The only question is if Windows 11 will launch in time for Alder Lake.

Alder Lake: Intel 12th Gen Core Golden Cove Microarchitecture (P-Core) Examined
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  • Gondalf - Thursday, August 19, 2021 - link

    You mean 5nm Zen 4 will have AVX512.
    Anyway wait and see if only on server cores or even in consumer, sure 5nm will give room for AVX512 in desktop cpus, but it is not for certain.
    The funny thing we are in front of a tight situation for both Intel and AMD.
    AMD can not go seriously on 5nm because there are not enough wafers around, Intel have to wait 7nm for new designs.
    Intersting times, if roadmaps are true, both AMD and Intel will are on a 5nm class process around at the same time, sometime at the end of 2022.
    We'll see the best one between two contenders.
    Reply
  • JayNor - Thursday, August 19, 2021 - link

    Looks like a Sapphire Rapids HEDT would be Intel's solution for pro consumers who want avx512. It would include bfloat16 support and AMX tiled matrix operations, which have not been available previously.

    An eight core Golden Cove HEDT chip with its dual avx512 and tiled matrix bfloat16 units enabled sounds like a decent upgrade from Ice Lake HEDT.
    Reply
  • mode_13h - Friday, August 20, 2021 - link

    Does SPR have BFloat16 in AVX-512, or just via AMX? I thought its AVX-512 is still not fully caught up with Cooper Lake. Reply
  • Kamen Rider Blade - Thursday, August 19, 2021 - link

    The desktop processor will have sixteen lanes of PCIe 5.0, which we expect to be split as x16 for graphics or as x8 for graphics and x4/x4 for storage. This will enable a full 64 GB/s bandwidth. Above and beyond this are another four PCIe 4.0 lanes for more storage. As PCIe 5.0 NVMe drives come to market, users may have to decide if they want the full PCIe 5.0 to the discrete graphics card or not

    Why won't they allow BiFurication of PCIe 5.0 = x12 + x4 as an option?

    x12 PCIe lanes is part of the PCIe spec, it should be better supported.

    Same with PCIe Gen 5.0 x12 + x2 + x2

    That can offer alot of flexibility in end user setups.
    Reply
  • mode_13h - Friday, August 20, 2021 - link

    The reality is that consumers don't need PCIe 5.0 x16. The benefits of even 4.0 x16 are small (but certainly real, in several cases).

    IMO, the best case for PCIe 5.0 would be x8 + x8 for multi-GPU setups. This lets you run dual-GPU, with each getting the same bandwidth as if it had a 4.0 x16 link.

    Unfortunately, they seem to have overlooked that obvious win, and all for the sake of supporting a use case we certainly won't see within the life of this platform: a SSD that can actually exceed 4.0 x4 speeds.
    Reply
  • Dug - Friday, August 20, 2021 - link

    As long as I can have 3 ssd's that can run full speed at PCIe 4.0, I'll be happy. Reply
  • mode_13h - Thursday, August 19, 2021 - link

    The Thread Director is intriguing. I wonder how much of the same information can be gleaned from the performance counter registers, although having an embedded microcontroller analyze it saves the OS from the chore of doing so.

    Can it raise interrupts, though? If not, then I don't see much point to enabling performance characterization in 30 microseconds, as that's way shorter than an OS timeslice.

    It should be an interesting target for new sidechannel attacks, as well.
    Reply
  • Jorgp2 - Thursday, August 19, 2021 - link

    Isn't it hardware feedback interface, not hardware frequency interface? Reply
  • eastcoast_pete - Thursday, August 19, 2021 - link

    To me, the star of the CPU cores is the "little" one, Gracemont. Question about AL in Ultrabooks: Why not an SoC with 4, 6, or 8 Gracemont cores plus some Xe Graphics, at least for the lower end? For most regular business use cases, that'll do just fine. The addition of AVX/AVX2 also means that certain effects for video conferencing, such as virtual backgrounds (Teams, other) is now possible with these beefed-up Atoms.
    And, on the other end of the spectrum, I agree with Ian that a 32 or more Gracemont-core CPU would work well if you want to run a lot of threads within a reasonable power envelope. @Ian: any chance you can get your hands on one of the CPUs specified for 5G base stations? Even the current, Tremont-based ones are exactly that: many Atom cores in one, specialized server CPU. Would be nice to see how those go.
    Reply
  • eastcoast_pete - Thursday, August 19, 2021 - link

    To be very precise: I meant an SoC without any "Cove" cores, just 4 or more Gracemonts. It'll do for many, especially business uses. Reply

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