Intel's Centrino CPU (Pentium-M): Revolutionizing the Mobile World

Productizing Banias - Introducing the Pentium-M

For those of you that still believe microprocessor architectures are decided upon by marketing folks first and then handed off to engineers to make, Banias should be all the proof necessary to convince you otherwise.

Intel's Pentium M Processor

The core is clearly not designed for high clock speeds and thus provided Intel's marketing with a very difficult job. How do you explain to end users that there's a new mobile processor on the market that is faster than a Pentium 4 clock for clock, and because of its high IPC it is actually faster than most of the higher clocked Pentium 4s?

Intel's marketing team came up with the idea of moving the focus away from the processor itself, and over to the entire mobile package - CPU, chipset and wireless adapter. Intel branded this package of three components as Centrino, with hopes that end users would walk into a store and request a Centrino laptop, instead of a xxGHz laptop.

While we'll talk about the other parts of the Centrino architecture what we've been focusing thus far on has been the CPU itself, which has been going by the codename Banias for years now. The final name of Banias is the Pentium-M and today is available in 6 different flavors; each of the Pentium-M chips have the exact same features, cache sizes, etc… and only differ according to operating frequency and voltages:

As you can gather by the table above, the Pentium-M features the same SpeedStep technology that we've seen from previous Intel CPUs. On battery power, the CPU will drop to a noticeably lower clock speed (600MHz in the case of all first generation Pentium-M CPUs). The difference between the Pentium-M's power management and other mobile Intel CPUs is mainly in the way sleep states are handled; whereas conventional mobile CPUs put various parts of the core to sleep when idle, the Pentium-M starts out in sleep mode and parts of it are woken up when necessary. Once again, the downside is that it takes a few clock cycles longer to get the appropriate units to wake up, but the power savings are non-trivial, and thus enable higher performance in the end by allowing for features like a 1MB on-die L2 cache or a higher clock speed.